Field
Various features relate to an integrated device package that includes a photo sensitive fill between a substrate and a die.
Background
FIG. 1 illustrates a conventional configuration of an integrated package that includes a die. Specifically, FIG. 1 illustrates an integrated device package 100 that includes a package substrate 101, a die 103, and a fill 130. The package substrate 101 includes several dielectric layers (e.g., dielectric layer 102), several interconnects (e.g., traces, vias, pads) 105, and a set of solder balls 115. The package substrate 101 may include an interconnect 111. The interconnect 111 may be a surface interconnect located on the surface of the package substrate 101 (e.g., on the surface of a dielectric layer of the package substrate). The interconnect 111 may be a trace and/or a pad.
As shown in FIG. 1, the die 103 is coupled to the package substrate 101 through a pillar 121, a solder 123, and the interconnect 111. The pillar 121 is coupled to the die 103. The pillar 121 may be a metal layer (e.g., a copper pillar). The fill 130 is located between the package substrate 101 and the die 103. The fill 130 encapsulates the pillar 121, the solder 123, and the interconnect 111. In some implementations, the fill 130 is a paste. The die 103 is coupled to the package substrate 101 by using a thermal compression flip chip (TCFC) process. The result of using a TCFC process is that it produces a laterally elongated solder 123, as shown in FIG. 1. Specifically, the elongated solder 123 has a lateral width that is greater than the width of the pillar 121 and/or the width of the interconnect 111. An elongated solder 123 is problematic in a package that includes high density, low pitch and/or low spacing interconnects because the elongated solder 123 may make physical contact with a nearby solder, pillar and/or interconnect causing a short in the package.
FIG. 2 illustrates another example of how solder may be formed between a die and a package substrate. As shown in FIG. 2, the die 103 is coupled to the package substrate 101 through the pillar 121, a solder 200, and the interconnect 111. A fill 230 is located between the package substrate 101 and the die 103. The fill 230 encapsulates the pillar 121, the solder 200, and the interconnect 111. The fill 230 is an under fill.
In FIG. 2, the die 103 is coupled to the package substrate 101 by using a mass reflow process. The result of using a mass reflow process is that it also produces a laterally elongated solder 200. Specifically, the elongated solder 200 has a lateral width that is greater than the width of the pillar 121 and/or the width of the interconnect 111. Moreover, the solder 200 couples to the side portions (e.g., side walls) of the interconnect 111. An elongated solder 200 is problematic in a package that includes high density, low pitch and/or low spacing interconnects because the elongated solder 200 may make physical contact with a nearby solder, pillar and/or interconnect causing a short in the package.
FIG. 3 illustrates yet another example of how solder may be formed between a die and a package substrate. Specifically, FIG. 3 illustrates a die 103 coupled to a package substrate 301 through a pillar 321, a solder 323, and an interconnect 311. A fill 330 is located between the package substrate 301 and the die 303. The fill 330 encapsulates the pillar 321, the solder 323, and the interconnect 311.
The pillar 321 has a width that is less than the width of the interconnect 311. The resulting solder 323 between the pillar 321 and the interconnect 311 is the solder 323 having a width that is greater than the width of the pillar 321. This results in unnecessary material (e.g., too much solder 323), resulting in higher cost of the integrated package. Moreover, at least a majority of the solder 323 has a dimension that is greater than the pillar 321.
Therefore, there is a need for an integrated device package that provides a design that is less likely to produce solder that will causes shorts, resulting in less defective integrated device packages. Ideally, such an integrated device package will have a better design and form factor, lower cost, while at the same time meeting the needs and/or requirements of mobile, wearable or portable computing devices.